ANALYSIS OF METHODS FOR HARDWARE AMOUNT REDUCTION IN THE COMBINED FSM SCHEME IMPLEMENTED IN THE CPLD

Abstract

The model of finite state machine (FSM) is used in a lot of cases of control unit design. In this
article a short review of the control unit models is given. The attention is paid to the model of combined finite state machine (CFSM), which is considered in detail. The main feature of the CFSM model is to combine
the Mealy and Moore models, which means the ability to form two corresponding types of output functions in
one cycle.
There is some optimization problem connected with CFSM synthesis, and choice of its solution depends
on the hardware base of implementation.
The modern hardware platform is represented by chips of programmable logic FPGA and CPLD.
CPLD type circuits are popular due to their availability. CPLD, like any other structure, has certain design
parameters, so the control algorithms that are implemented on CPLD, can be optimized for these parameters. The criteria of optimization may be different: reducing the power consumption of the FSM circuit, productivity increasing, etc. The choice of a priority criterion depends on the overall concept and the ultimate goal of the project. In this article we discuss the methods of logic circuit optimization of CFSM type
control unit. In our case the main criterion of optimization is the reduction of hardware amount.
The main task of this research is to reduce the hardware amount of combined FSM realization on the
CPLD. The architectural features of complex programmable logic device are analyzed. Based on the analysis, the basic model of the implementation of combined finite state machine in CPLD is proposed. The reduction of hardware amount of the CFSM scheme is directly related to the decreasing of terms number in the
Boolean functions system describing an automaton. The optimization methods for basic CFSM model are
proposed, such as: the method of decreasing the number of optimized terms relative to the output function;
the method of decreasing the number of terms relative to the classes of pseudoequivalence; the method of
output variables sets encoding.
Studies have been conducted to evaluate the effectiveness of each method. For the each discussed model
of CFSM, the states of the automaton have been encoded trivially, a direct structured table and functional
systems are developed. The resulting systems are represented by synthesized VHDL constructs and implemented in Altera MAX V chips, as well as Xilinx CoolRunner 2 and XC9500XL.
Based on the results of the study, it is clear that the most optimal combined FSM schemes are implemented in microcircuits Xilinx XC9500XL, and the most effective method is the method of combined FSM
synthesis with the output variable sets encoding

Author Biographies

Світлана Сергіївна Грушко, Zaporizhzhya National Technical University

assistant of the Department of Computer Systems and Networks,
Zaporizhzhya National Technical University

Ірина Яківна Зеленьова, Zaporizhzhya National Technical University

PhD, assistant professor of the Department of Computer Systems and
Networks, Zaporizhzhya National Technical University

Published
2018-06-26
How to Cite
Грушко, С., & Зеленьова, І. (2018). ANALYSIS OF METHODS FOR HARDWARE AMOUNT REDUCTION IN THE COMBINED FSM SCHEME IMPLEMENTED IN THE CPLD. Electrotechnic and Computer Systems, (28(104), 161-169. https://doi.org/10.15276/eltecs.28.104.2018.19
Section
Information systems and technologies